1. Field of the Invention
The present invention relates to a process for fabricating a field-effect transistor device implemented on a network of vertical nanowires, including a plurality of elementary transistors, each elementary transistor comprising a source electrode and a drain electrode each positioned at one end of a vertical nanowire of the network and connected by a channel and each elementary transistor including a gate electrode surrounding each vertical nanowire of the network, the drain, source and gate electrodes of the elementary transistors implemented on the nanowires are respectively connected to each other so as to form unique drain, source and gate electrodes of the transistor device.
The invention also relates to an electronic device comprising such transistor devices, and a processor comprising at least one such electronic device.
The development of microelectronics is based on the sizing of transistor devices, which, in addition to saving space, makes it possible to improve the performance of the devices.
Nevertheless, the sizing, i.e., the decrease in the dimensions, in particular the length of the gate of a transistor, creates difficulties in the production of said devices, research and development costs, and technological complexity, as well as limitations associated with the very physics of the devices. For example, the miniaturization of the gate of a transistor causes a control loss of the channel of the transistor, also called short channel effects, which deteriorates the performance of said transistor devices, for example by causing a high leakage current, a shift of the threshold voltage, etc., and destroys the inherent benefits of miniaturization.
2. Description of the Related Art
Thus, new gate architectures have been introduced to resolve this problem while improving the electrostatic control of the channel, using multi-gates.
It is known that the optimal electrostatic configuration is generated by a so-called “surrounding” gate around a small volume element of the semiconductor, for example a gate around a nanowire. The nearly perfect control of the short channel effects makes it possible in particular to demonstrate very low leakage currents for nanoscale gate lengths.
Nevertheless, the control current, i.e., the current passing through the transistor in the on state, remains low, as it is limited by the small cross-section of the nanowire. It is therefore crucial not to implement a transistor on a single wire or nanowire, but on a network of nanowires so as to combine excellent electrostatic control with a high current level in the on state.
Transistors can be integrated on horizontal or vertical networks. Horizontal networks are difficult to produce on large scales as they require stacking many layers and integrating transistor devices on those networks is even more complex: there are difficulties in defining a nanoscale gate on the different layers, difficulties in doping the source/drain areas, etc.
Vertical integration makes it possible to eliminate these problems. In fact, the dense networks are easier to produce using the top-down approach (etching) and the bottom-up approach (growth).
The production of nanoscale gates does not require a critical lithography step, for example electronic lithography, since the gate length is simply defined by the thickness of the deposited layer of the gate material.
The field-effect transistor devices implemented on a vertical nanowire network nevertheless have difficulties, for example in producing source (or drain) contacts at the bottom (or at the top) of the transistors, controlling parasitic gate/source-drain overlap capacitances, to produce sources/drains auto-aligned on the gate or to produce layers of insulating material, also called insulating spacers, between the source or the drain and the gate, the thickness and flatness of which must be controlled so as to ensure good control of parasitic overlap capacitances and to be able to reduce the gate length.
Documents US 2003/0189202 and U.S. Pat. No. 7,446,025 describe processes for fabricating field-effect transistor devices implemented on a network of vertical nanowires.
Nevertheless, these processes are relatively complex. In fact, they in particular comprise a step for forming a conductive layer for contact of the bottom on which catalysts are located to produce growth of the network of nanowires. However, it is known by those skilled in the art that it is extremely difficult to be able both to vertically grow nanowires with good reproducibility on a metal or silicide (i.e., without benefiting from the crystalline directions of the substrates) and to ensure good temperature resistance of the metal materials.
Furthermore, US 2003/0189202 does not describe a field-effect transistor device.
Additionally, the field-effect transistor device described in U.S. Pat. No. 7,446,025 does not have optimized capacities, since the insulation between the source (bottom contact) and the gate consists of the gate insulation, therefore with a small thickness causing extremely high source/gate coupling capacities.
Other processes for fabricating FET devices on networks of vertical nanowires are described in the literature. For example, M. Egard et al. in the article “Vertical InAs Nanowire Wrap Gate Transistors with ft>7 GHz and fmax>20 GHz”, NanoLetters, 10(3), pp. 809-812, 2010, uses an architecture presented by C. Thelander et al. in the article entitled “Development of a Vertical Wrap-Gated InAs FET”, IEEE Trans. on Elec. Dev., 55(11), pp 3030-3036, November 2008], V. Schmidt et al. in the article “Realization of a Silicon Nanowire Vertical Surround-Gate Field-Effect Transistor”, Small, 2(1), pp 85-88, January 2006 or by T. Tanaka et al. in the article entitled “Vertical Surrounding Gate Transistors Using Single InAs Nanowires Grown on Si Substrates” Appl. Phys. Express 3, 025003, 2010, which describe a process in which the topology of the gate is produced with a noticeable wave effect, greater than 50 nm, thereby preventing the miniaturization of the gate length while introducing parasitic capacitances between part of the gate and the nanowire. This wave phenomenon is inherent to the topology of the spacer insulation, which, in the vicinity of the nanowire, causes a rising or descending wave depending on the embodiment.